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| ksz8081rna/ksz8081rnd 10base - t/100base - tx phy with rmii support revision 1.1 linkmd is a registered trademark of m icrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com february 6, 2014 revision 1.1 general description the ksz8081rna is a single - supply 10base - t/100base - tx ethernet physical - layer transceiver for transmission and reception of data over standard cat - 5 unshielded twisted pair (utp) cable. the ksz8081rna is a highly - integrated phy solution . it reduces board cost and simplifies board layout by using on - chip termination resistors for the differential pairs and by integrating a low - noise regulator to supply the 1.2v core , and by offering 1.8/2.5/3.3v digital i/o interface support . the ksz8081r na offers the reduced media independent interface (rmii) for direct connection to rmii - compliant macs in ethernet processors and switches . a s the power - up default, the ksz8081rna uses a 25mhz crystal to generate all required clocks, including the 50mhz rmi i reference clock output for the mac. the ksz8081rnd is the version that takes in the 50mhz rmii reference clock as the power - up default. to facilitate system bring - up and debugging in production testing and in product deployment, parametric nand tree sup port enables fault detection between ksz8081rna i/os and the board. micrel?s linkmd ? tdr - based cable diagnostics identify faulty copper cabling. the ksz8081rna and ksz8081rnd are available in 24 - pin, lead - free qfn packages (see ? ordering information ?). data sheets and support documentation are available on micrel?s web site at: www.micrel.com . features ? single - chip 10base - t/100base - tx ieee 802.3 compliant ethernet t ransceiver ? rmii v1.2 interface support with a 50mhz reference clock output to mac, and an option to input a 50 mhz reference clock ? rmii b ack - to - b ack mode support for a 100mbps copper repeater ? mdc/mdio management i nterface for phy register configuration ? programmable interrupt o utput ? led outputs for link and activity status indication ? on - chip termination resistors for the differential pairs ? baseline wander c orrection ? hp auto mdi/mdi - x to reliably detect and correct strai ght - through and crossover cable connections with disable and enable option ? auto - negotiation to automatically select the highest link - up speed (10/100mbps) and duplex (half/full) ? power - down and power - saving modes ? linkmd tdr - based cable diagnostics to identif y faulty copper cabling ? parametric nand tree support for fa ult detect ion between chip i/os and the board functional diagram
micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 2 revision 1.1 features (continued) ? loopback modes for diagnostics ? single 3.3v power supply with vdd i/o options for 1.8v, 2.5v, or 3.3v ? built - in 1.2v regulator for core ? available in 24- pin (4mm x 4 mm) qfn package applications ? game c onsole ? ip p hone ? ip set - top b ox ? ip tv ? lom ? printer ordering information part number temperature range package lead finish wire bonding description KSZ8081RNACA 0c to 70c 24- pin qfn pb - free gold rmii with 25mhz crystal /clock input and 50mhz rmii ref_clk output (power - up default), commercial temperature, gold wire bonding ksz8081rnaia (1) ? 40c to 85c 24- pin qfn pb - free gold rmii with 25mhz crystal/clock input and 50mhz rmii ref_clk output (power - up default), industri al temperature, gold wire bonding ksz8081rndca 0c to 70c 24- pin qfn pb - free gold rmii with 50mhz clock input (power - up default), commercial temperature, gold wire bonding ksz8081rna -eval 0c to 70c 24- pin qfn pb - free ksz8081rna evaluation board (mou nted with ksz8081rna device in commercial temperature) ksz8081rnd -eval 0c to 70c 24- pin qfn pb - free ksz8081rnd evaluation board (mounted with ksz8081rnd device in commercial temperature) note: 1. contact factory for availability . micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 3 revision 1.1 revision history d ate summary of changes revision 11/ 5 /12 initial release of datasheet. 1.0 2/6/14 removed copper wire bonding part numbers from ordering information. added note for rxer (pin 17 ) and register 16h, bit [15] regarding a reserved factory mode. added serie s resistance and load capacitance for the 25mhz crystal selection criteria. 1.1 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 4 revision 1.1 contents list of fig ures .......................................................................................................................................................................... 6 list of tables ........................................................................................................................................................................... 7 pin configuration ..................................................................................................................................................................... 8 pin description ........................................................................................................................................................................ 9 strapping options ................................................................................................................................................................. 11 functional description: 10base - t/100base - tx transceiver ................................................................................................ 12 100base - tx transmit .......................................................................................................................................................................... 12 100base - tx receive ........................................................................................................................................................................... 12 scrambler/de - scrambler (100base - tx only) ...................................................................................................................................... 12 10base - t transmit .............................................................................................................................................................................. 12 10base - t receive ............................................................................................................................................................................... 13 pll clock synthesizer ........................................................................................................................................................................ 13 auto - negotiation .................................................................................................................................................................................. 13 rmii interface ........................................................................................................................................................................ 15 rmii signal definition .......................................................................................................................................................................... 15 rmii signal diagram ? 25/50mhz clock mode ................................................................................................................................... 16 back - to - back mode ? 100mbps copper repeater ............................................................................................................... 18 rmii back -to - back mode ..................................................................................................................................................................... 18 mii management (miim) interface ......................................................................................................................................... 19 interrupt (intrp) ................................................................................................................................................................... 19 hp auto mdi/mdi - x .............................................................................................................................................................. 19 straight cable ...................................................................................................................................................................................... 20 crossover cable .................................................................................................................................................................................. 20 loopback mode ..................................................................................................................................................................... 21 local (digital) loopback ...................................................................................................................................................................... 21 remote (analog) loopback ................................................................................................................................................................. 22 linkmd ? cable diagnostic .................................................................................................................................................... 23 nand tree support .............................................................................................................................................................. 23 nand tree i/o testing ....................................................................................................................................................................... 24 power management .............................................................................................................................................................. 24 power - saving mode ............................................................................................................................................................................ 24 energy - detect power - down mode ...................................................................................................................................................... 24 power - down mode .............................................................................................................................................................................. 24 slow - oscillator mode ........................................................................................................................................................................... 25 reference circuit for power and ground connections ......................................................................................................... 26 typical current/power consumption .................................................................................................................................... 27 transceiver (3.3v), digital i/os (3.3v) ................................................................................................................................................. 27 transceiver (3.3v), digital i/os (2.5v) ................................................................................................................................................. 27 transceiver (3.3v), digital i/os (1.8v) ................................................................................................................................................. 28 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 5 revision 1.1 register ma p ......................................................................................................................................................................... 29 register description .............................................................................................................................................................. 30 absolute maximum ratings .................................................................................................................................................. 39 operati ng ratings ................................................................................................................................................................. 39 electrical characteristics ....................................................................................................................................................... 39 timing diagrams ................................................................................................................................................................... 41 r mii timing ......................................................................................................................................................................................... 41 auto - negotiation timing ...................................................................................................................................................................... 42 mdc/mdio timing .............................................................................................................................................................................. 43 powe r- up/reset timing ...................................................................................................................................................................... 44 reset circuit .......................................................................................................................................................................... 45 reference circuits ? led strap - in pins ................................................................................................................................ 46 reference clock ? connection and selection ...................................................................................................................... 47 magnetic ? connection and selection .................................................................................................................................. 48 recommended land pattern ................................................................................................................................................ 50 package information ............................................................................................................................................................. 51 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 6 revision 1.1 list of figures figure 1. auto - negotiation flow chart ................................................................................................................................. 14 figure 2. ksz8081rna/rnd rmii interface (rmii ? 25mhz clock mode) ........................................................................ 17 figure 3. ksz8081rna/rnd rmii interface (rmii ? 50mhz clock mode) ........................................................................ 17 figure 4. ksz8081rna/rnd and ksz8081rna/rnd rmii back - to - back copper repeater ........................................... 18 figure 5. typical straight cable connection ....................................................................................................................... 20 figure 6. typical crossover cable connection ................................................................................................................... 21 figure 7. local (digital) loopback ....................................................................................................................................... 21 figure 8. remote (analog) loopback .................................................................................................................................. 22 figure 9. ksz8081rna/rnd power and ground connections .......................................................................................... 26 figure 1 0. rmii timing ? data received from rmii ............................................................................................................ 41 figure 11. rmii timing ? data input to rmii ....................................................................................................................... 41 figure 12. auto - negotiation fast l ink pulse (flp) timing ................................................................................................. 42 figure 13. mdc/mdio timing .............................................................................................................................................. 43 figure 14. power - up/reset timing ...................................................................................................................................... 44 figure 15. recommended reset circuit .............................................................................................................................. 45 figure 16. recommended reset circuit for interfacing with cpu/fpga reset output ..................................................... 45 figure 17. reference circuits for led strapping pins ......................................................................................................... 46 figure 18. 25mhz crystal/oscillator reference clock connection ..................................................................................... 47 figure 19. 50mhz oscillator reference clock connection ................................................................................................. 47 figure 20. typical magnetic interface circuit ....................................................................................................................... 48 figure 21. recommended land pattern, 24 - pin (4mm 4mm) qfn ................................................................................. 50 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 7 revision 1.1 list of tables table 1. rmii signal definition ............................................................................................................................................. 15 table 2. rmii signal connection for rmii back - to - back mode (100base - tx copper repeater) ...................................... 18 table 3. mii management frame format for the ksz8081rna/rnd ................................................................................ 19 table 4. mdi/mdi - x pin definition ....................................................................................................................................... 20 table 5. nand tree test pin order for ksz8081rna/rnd .............................................................................................. 23 table 6. ksz8081rna/rnd power pin description ........................................................................................................... 26 table 7. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) ............................................................ 27 table 8. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 2.5v) ............................................................ 27 table 9. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) ............................................................ 28 table 10. rmii timing parameters ? ksz8081rna/rnd (25mhz input to xi pin, 50mhz output from ref_clk pin) .... 41 table 11. rmii timing parameters ? ksz8081rna/rnd (50mhz input to xi pin) ............................................................ 41 table 12. auto - negotiation fast link pulse (flp) timing parameters ............................................................................... 42 table 13. m dc/mdio timing parameters ........................................................................................................................... 43 table 14. power - up/reset timing parameters ................................................................................................................... 44 table 15. 25mhz crystal / reference clock selection criteria ........................................................................................... 47 table 16. 50mhz oscillator / reference clock selection criteria ....................................................................................... 47 table 17. magnetics selection criteria ................................................................................................................................ 49 table 18. compatible single - port 10/100 magnetics ........................................................................................................... 49 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 8 revision 1.1 pin configuration 24- pin (4mm 4mm) qfn micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 9 revision 1.1 pin descriptio n pin number pin name type (1) pin function 1 vdd_1.2 p 1.2v core v dd (power supplied by ksz8081rna/ksz8081rnd ) decouple with 2.2f and 0.1f capacitors to ground. 2 vdda_3.3 p 3.3v analog v dd 3 rxm i/o physical receive or transmit signal ( ? differential) 4 rxp i/o physical receive or transmit sign al (+ differential) 5 txm i/o physical transmit or receive signal ( ? differential) 6 txp i/o physical transmit or receive signal (+ differential) 7 xo o crystal feedback for 25mhz crystal this pin is a no connect if an oscillator or external clock sourc e is used. 8 xi i rmii ? 25mhz mode: 25mhz 50ppm crystal / oscillator / external clock input rmii ? 50mhz mode: 50mhz 50ppm oscillator / external clock input for unmanaged mode (power - up default setting), ksz8081rna takes in the 25mhz crystal/clock o n this pin. ksz8081rnd takes in the 50mhz clock/on this pin. after power - up, both the ksz8081rna and ksz8081rnd can be programmed to either the 25mhz mode or 50mhz mode using phy register 1fh bit [7]. see also ref_clk (pin 16). 9 rext i set phy transmit output current connect a 6.49k resistor to ground on this pin. 10 mdio ipu/opu management interface (mii) data i/o this pin has a weak pull - up, is open- drain , and requires an external 1.0k pull - up resistor. 11 mdc ipu management interface (mii) clock input this cloc k pin is synchronous to the mdio data pin. 12 rxd1 ipd/o rmii receive data output[1] (2) 13 rxd0 ipu/o rmii receive data output[0] (2) 14 vddio p 3.3v, 2.5v, or 1.8v digital v dd 15 crs_dv / phyad[1:0] ipd/o rmii mode: ca rrier sense/receive data valid o ut put / config mode: the pull - up/pull - down value is latched as phyad[1:0] at the de- assertion of reset. see the ? strapping options ? section for details. note: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. ipu = input with internal pull - up (see ? electrical characteristics ? for value). ipu/o = input with internal pull - up (see ? electrical characteristics ? for value) d uring power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (see ? electrical characteristics ? for value) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see ? electrical characteristics ? for value) and output with internal pull - up (see ? electrical characteristics ? for value). micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 10 revision 1.1 pin description (continued) pin number pin name t ype (1) pin function 16 ref_clk ipd/o rmii ? 25mhz mode: this pin provides the 50mhz rmii reference clock output to the mac. rmii ? 50mhz mode: this pin is a no connect. for unmanaged mode (power - up default setting), ksz8081rna is in rmii ? 25mhz mod e and outputs the 50mhz rmii reference clock on this pin. ksz8081rnd is in rmii ? 50mhz mode and does not use this pin. after power - up, both ksz8081rna and ksz8081rnd can be programmed to either 25mhz mode or 50mhz mode using phy register 1fh bit [7] . see also xi (pin 8). 17 rxer ipd/o rmii receive error output at the de - assertion of reset, this pin needs to latch in a pull - down value for normal operation. if mac side pulls this pin high, see register 16h, bit [15] for solution. 18 intrp ipu/opu int errupt output: programmable interrupt output this pin has a weak pull - up, is open drain, and requires an external 1.0k? pull - up resistor. 19 txen i rmii transmit enable input 20 txd0 i rmii transmit data input[0 ] (3) 21 txd1 i /o rmii transmit data input [1] (3) nand tree mode: nand tree output pin 22 gnd gnd ground 23 led0 / anen_speed ipu/o led output: programmable led0 output config mode: latched as auto - negotiation enable (register 0h, bit [12]) and speed (register 0h, bit [13]) at the de - assertion of reset. see the ? strapping options ? section for details. the led0 pin is programmable using register 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no l ink high off link low on activity toggle blinking led mode = [01] link pin state led definition no l ink high off link low on led mode = [10], [11] reserved 24 rst# ipu chip reset (active low) paddle gnd gnd ground notes: 2. rmii rx mode: the rxd[1:0] bits are synchronous with the 50mhz rmii reference clock. for each clock period in which crs_dv is asserted, two bits of recovered data are sent by the phy to the mac. 3. rmii tx m ode: the txd[1:0] bits are synchronous with the 50mhz rmii reference clock. for each clock period in which txen is asserted, two bits of data are received by the phy from the mac. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 11 revision 1.1 strapping option s pin number pin name type (1) pin function 15 phyad[1:0] ipd /o the phy address is latched at the de - assertion of reset and is configurable to either one of the following two values: pull - up = phy address is set to 00011b (0x3h) pull - down (default) = phy address is set to 00000b (0x0h) phy address bits [4:2] are set to 000 by default. 23 anen_speed ipu/o auto - negotiation enable and speed mode pull - up (default) = enable auto- negotiation and set 100mbps speed pull - down = disable auto- negotiation and set 10mbps speed at the de - assertion of reset, this pin value is latched into register 0h bit [12] for auto - negotiation enable/disable, register 0h bit [13] for the speed select, and register 4h (auto - negotiation advertisement) for the speed capability support. note: 1. ipu/o = input with internal pull - up (see ? electrical characteristics ? for value) during power - u p/reset; output pin otherwise. ipd/o = input with internal pull - down (see ? electrical characteristics ? for value) during power - up/reset; output pin otherwise. the phyad[1:0] strap - in pin is latched at the de - asserti on of reset. in some systems, the rmii mac receive input pins may drive high/low during power - up or reset, and consequently cause the phyad[1:0] strap - in pin, a shared pin with the rmii crs_dv signal, to be latched to the unintended high/low state . in this case an external pull - up (4.7 k?) or pull - down (1.0k? ) should be added on the phyad[1:0] strap - in pin to ensure that the intended value is strapped - in correctly. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 12 revision 1.1 functional description: 10base- t/100base - tx transceiver the ksz8081rna is an integrated singl e 3.3v supply fast ethernet transceiver. it is fully compliant with the ieee 802.3 specification , and reduces board cost and simplifies board layout by using on - chip termination resistors for the two differential pairs and by integrating the regulator to s upply the 1.2v core. on the copper media side, the ksz8081rna supports 10base - t and 100base - tx for transmission and reception of data over a standard cat - 5 unshielded twisted pair (utp) cable, and h p a uto mdi/mdi - x for reliable detection of and correction for straight - through and crossover cables. on the mac processor side, the ksz8081rna offers the reduced media independent interface (rmii) for direct connection with rmii - compliant ethernet mac processors and switches the mii management bus option gives th e mac processor complete access to the ksz8081rna control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll for phy status change. a s the power - up default, the ksz8081rna uses a 25mhz crystal to generate all required clocks, including the 50mhz rmii reference clock output for the mac. the ksz8081rnd version uses the 50mhz rmii reference clock as the power - up default. the ksz8081rna /rnd is used to refer to both ksz8081rna and ksz8081rn d versions in this data sheet. 100base - tx transmit the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b encoding, scrambling, nrz - to - nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel - to - serial conversion, which co nverts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding and followed by a scrambler. the serialized data is further converted from nrz - to - nrzi format, and then transmitted in mlt3 cu rrent output. the output current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp - pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated i nto the 100base - tx transmitter. 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - paral lel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adj ust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an on going process and self - adjusts against environmental changes such as temperature variations. next, the equ alized signal goes through a dc - restoration and data - conversion block. the dc - restoration circuit compensate s for the effect of baseline wander and im prove s the dynamic range. the diff erential data - conversion circuit converts mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock - recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is th en used to convert the nrzi signal to nrz format. this signal is sent through the de - scrambler , then the 4b/5b decoder. finally, the nrz serial data is converted to mii format and provided as the input data to the mac. scrambler/de - scrambler (100base - tx o nly) the scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (emi) and baseline wander. the de - scrambler recovers the scrambled signal. 10base - t transmit the 10base - t drivers are incorporated with the 100ba se - tx drivers to allow for transmission using the same magnetic. the drivers perform internal wave - shaping and pre - emphasis, and output 10base - t signals with a typical amplitude of 2.5v peak. the 10base - t signals have harmonic contents that are at least 27 db below the fundamental frequency when driven by an all - ones manchester - encoded signal. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 13 revision 1.1 10base - t receive on the receive side, input buffer and level detecting squelch circuits are used . a differential input receiver circuit and a phase - lock ed loop ( pll ) p erforms the decoding function. the manchester - encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects si gnals with levels less than 400 mv , or with short pulse widths , to prevent noise at the rxp and rxm inputs from falsel y trigger ing the decoder. when the input exceeds the squelch limit, the pll locks onto the i ncoming signal and the ksz8081rna/rnd decodes a data frame. the receive clock is kept active during idle periods between data reception s . pll clock synthesizer the ksz8081rna/rnd in rmii ? 25mhz clock mode generates all internal clocks and all external clocks for system timing from an external 25mhz crystal, oscillator, or reference clock. for the ksz8081rna/rnd in rmii ? 50mhz clock mode, these clocks are generated from an external 50mhz oscillator or system clock. auto - negotiation the ksz8081rna/rnd conforms to the auto - negotiation protocol, defined in clause 28 of the ieee 802.3 specification. auto - negotiation allows unshielded twisted pair ( utp ) link partners to select the highest common mode of operation. during auto - negotiation, link partners advertise capabilities across the utp link to each other and then compare their own capabilities with those they received from their link partners. the highest speed and d uplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest priority. ? priority 1: 100base - tx, full - duplex ? priority 2: 100base - tx, half - du plex ? priority 3: 10base - t, full - duplex ? priority 4: 10base - t, half - duplex if auto - negotiation is not supported or the ksz8081rna/rnd link partner is forced to bypass auto - negotiation, then the ksz8081rna/rnd sets its operating mode by observing the signa l at its receiver. this is known as parallel detection, which allows the ksz8081rna/rnd to establish a link by listening for a fixed signal protocol in the absence of the auto - negotiation advertisement protocol. auto - negotiation is enabled by either hardwa re pin strapping ( anen_speed, pin 23 ) or software (register 0h, bit [12]). by default, auto - negotiation is enabled after power - up or hardware reset. after that , auto - negotiation can be enabled or disabled by register 0h, bit [12]. if auto - negotiation is d isabled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8]. the auto - negotiation link - up process is shown in figure 1 . micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 14 revision 1.1 figure 1 . auto - negotiation flow chart micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 15 revision 1.1 r mii interface the reduced media independent interface (rmii) specifies a low pin count media independent interface (mii). it provides a common interface between physical layer and mac layer devices, and has the following key characteristics : ? pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50mhz reference clock). ? 10mbps and 100mbps data rates are supported at both half - and full - duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 2 bits wide, a dibit. r m ii signal definition table 1 describes the r mii signals. refer to rmii specification v1.2 for detailed information . r mii signal name direction (with respect to phy, ksz8081rna/rnd signal) direction (with respect to mac) description ref_clk output (25mhz clock mode) / micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 16 revision 1.1 while carrier de tection criteria are met, crs_dv remains asserted continuously from the first recovered dibit of the frame through the final recovered dibit. it is negated before the first ref_clk that follows the final dibit. the data on rxd[1:0] is considered valid afte r crs_dv is asserted. however, because the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] is 00 until receive signals are proper ly decod ed . receive data[1:0] (rxd[1:0]) rxd[1:0] transitions synchronously with respect to ref_c lk. for each clock period in which crs_dv is asserted, rxd[1:0] transfers two bits of recovered data from the phy. rxd[1:0] is 00 to indicate idle when crs_dv is de- asserted. the mac ignores values other than 00 on rxd[1:0] while crs_dv is de - asserted. rec eive error (rxer) rxer is asserted for one or more ref_clk periods to indicate that a symbol error (for example, a coding error that a phy can detect that may otherwise be undetectable by the mac sub - layer) was detected somewhere in the frame being transfe rred from the phy. rxer transitions synchronously with respect to ref_clk . while crs_dv is de - asserted, rxer has no effect on the mac. collision detection (col) the mac regenerates the col signal of the mii from txen and crs_dv. r mii signal diagram ? 25/5 0mhz clock mode the ksz8081rna/rnd rmii pin connections to the mac for 25mhz c lock m ode are shown in figure 2 . the connections for 50mhz clock mode are shown in figure 3 . rmii ? 25mhz clock mode the ksz8081rna is configured to rmii ? 25mhz clock mode after it is powered up or hardware reset with the following: ? a 25mhz crystal connected to xi, xo (pins 8, 7), or an external 25mhz clock source (oscillator) connected to xi th e ksz8081rnd can optionally be configured to rmii ? 25mhz clock mode after it is powered up or hardware reset and software programmed with the following: ? a 25mhz crystal connected to xi, xo (pins 8, 7), or an external 25mhz clock source (oscillator) connec ted to xi ? register 1fh, bit [7] programmed to ? 1 ? to select rmii ? 25mhz clock mode micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 17 revision 1.1 figure 2 . ksz8081rna/rnd rmii interface ( rmii ? 25mhz clock mode) r mii ? 5 0 mhz clock mode the ksz8081rnd is configured to rmii ? 50mhz clock mode after it is powered up or hardware reset with the following: ? an external 50mhz clock source (oscillator) connected to xi (pin 8) the ksz8081rna can optionally be configured to rmii ? 50mhz clock mode after it is powered up or hardware reset and soft ware programmed with the following: ? an external 50mhz clock source (oscillator) connected to xi (pin 8) ? register 1fh, bit [7] programmed to ?1? to select rmii ? 50mhz clock mode figure 3 . ksz8081rna/rnd rmii interface (rmii ? 50mhz clock mode ) micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 18 revision 1.1 back -to- back mode ? 100mbps copper repeater two ksz8081rna/rnd devices can be connected back - to - back to form a managed 100base - tx copper repeater. figure 4 . ksz8081rna/rnd and ksz8081rna/rnd rmii back -to -ba ck copper repeater rmii back - to - back mode in rmii back - to - back mode, a ksz8081rna/rnd interfaces with another ksz8081rna/rnd to provide a 100mbps copper repeater solution. t he ksz8081rna/rnd devices are configured to rmii back - to - back mode after power - up or reset , and software programming, with the following: ? a common 50mhz reference clock connected to xi (pin 8) ? register 1fh, bit [7] programmed to ?1? to select rmii ? 50mhz clock mode for ksz8081rna (ksz8081rnd is set to rmii ? 50mhz clock mode as the de fault after power up or hardware reset) ? register 16h, bits [6] and [1] programmed to ?1? and ?1?, respectively, to enable rmii back - to - back mode. ? rmii signals connected as shown in table 2 ksz8081rna/rnd (100base - tx copper) [device 1] ksz8081rna/rnd (100base - tx copper) [device 2] pin name pin number pin type pin name pin number pin type crs_dv 15 output txen 19 input rxd1 12 output txd1 21 input rxd0 13 output txd0 20 input txen 19 input crs_dv 15 output txd1 21 input rxd1 12 output txd0 20 input rxd0 13 output table 2 . rmii signal connection for rmii back -to - back mode (100base- tx copper repeater) micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 19 revision 1.1 mii management (miim) interface the ksz8081rna/rnd supports the ieee 802.3 mii m anag ement i nterface, also known as the management data input/ output (mdio) i nterface. this interface allows an upper - layer device , such as a mac processor, to monitor and control the state of the ksz8081rna/rnd . an external device with miim capability is used to read the phy status and/or configure the phy settings. more detail s about the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates the clock l ine (mdc) and the data line (mdio). ? a specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communica te with one or more phy devices. ? a set of 16 - bit mdio registers. r egisters [0:8] are st andard registers, and their functions are defined in the ieee 802.3 specification. the additional registers are provided for expanded functionality. see the ? register map ? section for details. the ksz8081rna/rnd suppor ts only two unique phy addresses. the phyad[1:0] strapping pin is used to select either 0h or 3h as the unique phy address for the ksz8081rna/rnd device. phy address 0h is defined as the broadcast phy address according to the ieee 802.3 specification, and can be used to read/write to a single phy device, or write to multiple phy devices simultaneously. for the ksz8081rna/rnd, phy address 0h defaults to the broadcast phy address after power - up, but phy address 0h can be disabled as the broadcast phy address using software to assign it as a unique phy address. for applications that require two ksz8081rna/rnd phys to share the same mdio interface with one phy set to address 0h and the other phy set to address 3h, use phy address 0h (defaults to broadcast after power - up) to set both phys? register 16h, bit [9] to ?1? to assign phy address 0h as a unique (non - broadcast) phy address . table 3 shows the mii m anagement frame format for the ksz8081rna/rnd . preamble start of f rame read/write op code phy address bits [4:0] reg address bits [4:0] ta dat a bits [15:0] idle read 32 1?s 01 10 000 aa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 000 aa rrrrr 10 dddddddd_dddddddd z table 3 . mii management f rame format for the ksz8081rna/rnd interrupt (intrp) intrp (pin 18 ) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the ksz8081rna/rnd phy register. bits [15:8] of register 1bh are the interrupt control bits to enable and disable the conditions for asserting the intrp signal. bits [7:0] of r egister 1bh are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading r egister 1bh. bit [9] of r egister 1fh sets the interrupt level to active high or active low. the default is active low. the mii management bus option gives the mac processor complete access to the ksz8081rna/rnd control and status registers. additionally, a n interrupt pin eliminates the need for the processor to poll the phy for status change. hp auto mdi/mdi -x hp auto mdi/mdi - x configuration eliminates the need to decide whether to use a straight cable or a crossover cable between the ksz8081rna/rnd and it s link partner. this feature allows the ksz8081rna/rnd to use either type of cable to connect with a link partner that is in either mdi or mdi - x mode. the auto - sense function detects transmit and rece ive pairs from the link partner and assigns transmit and receive pairs to the ksz8081rna/rnd accordingly. hp auto mdi/mdi - x is enabled by default. it is disabled by writing a ?1? to register 1fh, bit [13]. mdi and mdi - x mode is selected by register 1fh, bit [14] if hp auto mdi/mdi - x is disabled. an isolation tr ansformer with symmetrical transmit and receive data paths is recommended to support a uto mdi/mdi - x. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 20 revision 1.1 table 4 shows how the ieee 802.3 standard defines mdi and mdi - x. mdi mdi -x rj - 45 pin signal rj - 45 pin signal 1 tx+ 1 rx+ 2 tx ? 2 rx ? 3 rx+ 3 tx+ 6 rx ? 6 tx ? table 4 . mdi/mdi - x pin definition straight cable a straight cable connects a n mdi device to a n mdi - x device, or a n mdi - x device to a n mdi device. figure 5 shows a typical straight cable connection between a nic card (mdi device) and a switch or hub (mdi - x device). figure 5 . typical straight cable connection crossover cable a crossover cable connects a n mdi devi ce to another mdi device, or a n mdi - x device to another mdi - x device. figure 6 shows a typical crossover cable connection between two switches or hubs (two mdi - x devices). micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 21 revision 1.1 figure 6 . ty pical crossover cable connection loopback mode the ksz8081rna/rnd supports the following loopback operations to verify analog and/or digital data paths. ? local (d igital) l oopback ? remote (a nalog) l oopback local (digital) loopback this loopback mode checks t he rmii transmit and receive data paths between the ksz8081rna/rnd and the external mac, and is s u pported for both speeds (10/100 mbps) at full - duplex. the loopback data path is shown in figure 7 . 1. the rmii mac trans mits frames to the ksz8081rna/rnd . 2. frames are wrapped around inside the ksz8081rna/rnd . 3. the ksz8081rna/rnd transmits frames back to the rmii mac. figure 7 . local (digital) loopback micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 22 revision 1.1 the following programming action and registe r settings are used for local l oopback mode. for 10/1 00 mbps loopback, set r egister 0h, ? bit [14] = 1 // enable local l oopback mode ? bit [13] = 0/1 // select 10mbps /100mbps speed ? bit [12] = 0 // disable a uto - n egotiation ? bit [8] = 1 // select full - du plex mode remote (analog) loopback this loopback mode checks the line (differential pairs, transformer, rj - 45 connector, ethernet cable) transmit and receive data paths between the ksz8081rna/rnd and its link partner, and is s upported for 100 base - t x full - d uplex mode only. the loopback data path is shown in figure 8 . 1. the fast ethernet (100base - tx) phy l ink p artner transmits frames to the ksz8081rna/rnd . 2. frames are wrapped around inside the ksz8081rna/rnd . 3. the ksz8081 rna/rnd transmits frames back to the fast ethernet (100base - tx) phy l ink p artner. figure 8 . remote (analog) loopback the following programming steps and register settings are used for remote l oopback mode. 1. set register 0h, ? b its [13] = 1 // select 10 0mbps speed ? bit [12] = 0 // disable auto - n egotiation ? bit [8] = 1 // selec t full - duplex mode or just auto - negotiate and link up at 100base - tx full - duplex mode with the link partner. 2. set register 1 f h, ? bit [ 2 ] = 1 // enable remote l oopback mode micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 23 revision 1.1 linkmd ? cable diagnostic the linkmd function uses time - domain reflectometry (tdr) to analyze the cabling plant for common cabling problems . these include open circuits, short circuits , and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi or mdi - x pair , then analyzing the shape of the reflected signal to determine the type of fault . the time duration for the reflected signal to return provides the approximate distance to the cabling faul t . the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 1dh, the linkmd control/statu s r egister, in conjunction with register 1fh, the phy control 2 r egister. the latter register is used to disable a uto mdi/mdi - x and to select either mdi or mdi - x as the cable differential pair for testing. nand tree support the ksz8081rna/rnd provides parametric nand t ree support for fault detection betw een chip i/os and board. the nand tree is a chain of nested nand gates in which each ksz8081rna/rnd digital i/o (nand tree input) pin is an input to one nand gate along the chain. at the end of the chain, the txd1 pin provides the output for the nested nan d gates. the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving each nand tree input pin low, sequentially , according to the nand tree pin order ? checking the nand tre e output to make sure there is a toggl e high - to - low or low - to - high for each nand tree input driven low table 5 list s the nand tree pin order . pin number pin name nand tree description 10 mdio input 11 mdc input 12 rxd1 input 13 rxd0 input 15 crs _dv input 16 ref_clk input 18 intrp input 19 txen input 23 led0 input 20 txd0 input 21 txd1 output table 5 . nand tree test pin order for ksz8081rna/rnd micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 24 revision 1.1 nand tree i/o testing use t he following procedure to check for faults on the ksz8081rna/rnd digital i/o pin connections to the board: 1. enable nand tree mode by setting register 16h, bit [5] to ?1? . 2. use board logic to drive all ksz8081rna/rnd nand tree input pins high. 3. use board logic to drive each nand tree input pin, in ksz 8081rna/rnd t ree pin order, as follow s : a. toggle the first pin (mdio) from high to low, and verify that the tdx1 pin switch es from high to low to indicate that the first pin is connected properly. b. leave the first pin (mdio) low. c. toggle the second pin (mdc) f rom high to low, and verify that the txd1 pin switch es from low to high to indicate that the second pin is connected properly. d. leave the first pin (mdio) and the second pin (mdc) low. e. toggle the third pin from high to low, and verify that the txd1 pin swit ch es from high to low to indicate that the third pin is connected properly. f. continue with this sequence until all ksz8081rna/rnd nand tree input pins have been toggled. each ksz8081rna/rnd nand tree input pin must cause the txd1 output pin to toggle high - to - low or low - to - high to indicate a good connection. if the txd1 pin fails to toggle when the ksz8081rna/rnd input pin toggles from high to low, the input pin has a fault. power management the ksz8081rna/rnd incorporates a number of power - management modes and features that provide methods to consume less energy. these are discussed in the following sections. power - saving mode power - s aving m ode is used to reduce the transceiver power consumption when the cable is unplugged. it is enabled by writing a ?1? to register 1fh, bit [10], and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). in this mode, the ksz8081rna/rnd shuts down all transceiver blocks except the transmitter, energy detect , and pll circuits. by default , power - saving m ode is disabled after power - up. energy - detect power - down mode energy - detect power - down (edpd) m ode is used to further reduce transceiver power con sumption when the cable is un plugged. it is enabled by writing a ?0? to register 18h, bit [11] , and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). edpd m ode works with the pll off (set by writing a ?1? to register 10h, bit [4] to automatically turn the pll off in edpd m ode) to turn off all ksz8081rna/rn d transceiver blocks ex cept the transmitter and energy - detect circuits. power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. the periodic transmission of link pulses i s needed to ensure two link partners in the same low power state and with auto mdi/mdi - x disabled can wake up when the cable is connected between them. by default, energy - detect power - down m ode is disabled after power - up. power - down mode power - down m ode is used to power down the ksz8081rna/rnd device when it is not in use after power - up. it is enabled by writing a ?1? to register 0h, bit [11]. in this mode, the ksz8081rna/rnd disables all internal functions except the mii management interface. t he ksz8081r na/rnd exits (disables) power - down m ode after register 0h, bit [11] is set back to ? 0 ? . micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 25 revision 1.1 slow - oscillator mode slow - oscillator m ode is used to disconnect the input reference crystal/clock on xi ( pin 8 ) and select the on - chip slow oscillator when the ksz8081r na/rnd device is not in use after power - up. it is enabled by writing a ?1? to register 11h, bit [5]. slow - o scillator mode works in conjunction with power - down m ode to put the ksz8081rna/rnd device in the lowest power state , with all internal functions disa bled except the mii management interface. to properly exit this mode and return to normal phy operation, use the following programming sequence: 1. disable slow - o scillator m ode by writing a ?0? to register 11h, bit [5]. 2. disable power - d own m ode by writing a ?0 ? to register 0h, bit [11]. 3. initiate software reset by writing a ?1? to register 0h, bit [15]. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 26 revision 1.1 reference circuit for power and ground connections the ksz8081rna/rnd is a single 3.3v supply device with a built - in regulator to supply the 1.2v core. the pow er and ground connections are shown in figure 9 and table 6 for 3.3v vddio. figure 9 . ksz8081rna/rnd power and ground connections power pin pin number description vdd_1.2 1 decouple with 2.2 f and 0.1 f capacitors to ground. vdda_3.3 2 connect to board?s 3.3v supply through a ferrite bead. decouple with 22 f and 0.1 f capacitors to ground. vddio 14 connect to board?s 3.3v supply for 3.3v vd dio. decouple with 22 f and 0.1 f capacitors to ground. table 6 . ksz8081rna/rnd power pin description micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 27 revision 1.1 typical current/power consumption table 7 through table 9 show typical values for current consumption by the transce iver (vdda_3.3) and digital i/o (vddio) power pins and typical values for power consumption by the ksz8081rna/rnd device for the indicated nominal operating voltage combinations . th ese current and power consumption values include the transmit driver current and on - chip regulator current for the 1.2v core. transceiver (3.3v), digital i/os (3.3v) condition 3.3v transceiver (vdda_3.3) 3.3v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 12 152 100base - tx full - duplex @ 100% utilization 34 13 155 10base - t link - up (no traffic) 14 11 82.5 10base - t full - duplex @ 100% utilization 30 11 135 power - saving mode (reg. 1fh, bit [10] = 1) 14 10 79.2 edpd mod e (reg. 18h, bit [11] = 0) 10 10 66.0 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.77 1.54 17.5 software power - down mode (reg. 0h, bit [11] =1) 2.59 1.51 13.5 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillato r mode (reg. 11h, bit [5] =1) 1.36 0.45 5.97 table 7 . typical current /power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) transceiver (3.3v), digital i/os (2.5v) condition 3.3v transceiver (vdda_3.3) 2.5v digital i/os (vddio) tot al chip power ma ma mw 100base - tx link - up (no traffic) 34 12 142 100base - tx full - duplex @ 100% utilization 34 13 145 10base - t link - up (no traffic) 15 11 77.0 10base - t full - duplex @ 100% utilization 27 11 117 power - saving mode (reg. 1fh, bit [10] = 1) 15 10 74.5 edpd mode (reg. 18h, bit [11] = 0) 11 10 61.3 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.55 1.35 15.1 software power - down mode (reg. 0h, bit [11] =1) 2.29 1.34 10.9 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.15 0.29 4.52 table 8 . typical current/ power consumption (vdda_3.3 = 3.3v, vddio = 2.5v) micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 28 revision 1.1 transceiver (3.3v), digital i/os (1.8v) condition 3.3v transceiver (vdda_3.3) 1.8v di gital i/os ( vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 11 132 100base - tx full - duplex @ 100% utilization 34 12 134 10base - t link - up (no traffic) 15 10 67.5 10base - t full - duplex @ 100% utilization 27 10 107 power - saving mode ( reg. 1fh, bit [10] = 1) 15 9.0 65.7 edpd mode (reg. 18h, bit [11] = 0) 11 9.0 52.5 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 4.05 1.21 15.5 software power - down mode (reg. 0h, bit [11] =1) 2.79 1.21 11.4 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.65 0.19 5.79 table 9 . typical current / power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 29 revision 1.1 register map register number (hex) description 0h basic cont rol 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto - negotiation advertisement 5h auto - negotiation link partner ability 6h auto - negotiation expansion 7h auto - negotiation next page 8h link partner next page ability 9h reserved 10h d igital reserved control 11h afe control 1 12h ? 14h reserved 15h rxer counter 16h operation mode strap override 17h operation mode strap status 18h expanded control 19h ? 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd control/s tatus 1eh phy control 1 1fh phy control 2 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 30 revision 1.1 register description address name description mode (1) default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self - cleared after a ?1? is written to it. rw/sc 0 0 .14 loop back 1 = loopback mode 0 = normal operation rw 0 0.13 speed select 1 = 100mbps 0 = 10mbps this bit is ignored if auto - negotiation is enabled (register 0.12 = 1). rw set by the anen_ speed strapping pin. see the ? str apping options ? section for details. 0.12 auto - negotiation enable 1 = enable auto - negotiation process 0 = disable auto - negotiation process if enabled, the auto - negotiation result overrides the settings in register s 0.13 and 0.8. rw set by the anen_speed strapping pin. see the ? strapping options ? section for details . 0.11 power - down 1 = power - down mode 0 = normal operation if software reset (registe r 0.15) is used to exit power -d own mode (register 0.11 = 1), two software reset writes (re gister 0.15 = 1) are required. the first write clears power -d own mode; the second write resets the chip and re - latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw 0 0.9 restart auto - negotiation 1 = restart auto - negotiation process 0 = normal operation. this bit is self - cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full - duplex 0 = half - duplex rw 1 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:0 reserved reserved ro 000_0000 register 1h ? basic status 1.15 100base -t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base - tx full - duplex 1 = capable of 100mbps full - duplex 0 = not capable of 100mbps full - duplex ro 1 1.13 100base -tx half - duplex 1 = capable of 100mbps half - duplex 0 = not capable of 100mbps half - duplex ro 1 note: 1. rw = read/write. ro = read only. sc = self - cleared. lh = latch high. ll = latch low. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 31 revision 1.1 register description (continued) address name description mode (1) defaul t register 1h ? basic status 1.12 10base -t full - duplex 1 = capable of 10mbps full - duplex 0 = not capable of 10mbps full - duplex ro 1 1.11 10base -t half - duplex 1 = capable of 10mbps half - duplex 0 = not capable of 10mbps half - duplex ro 1 1.10:7 reserved reserved ro 000_0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto - negotiation complete 1 = auto - negotiation process completed 0 = auto - negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fau lt ro/lh 0 1.3 auto - negotiation ability 1 = can perform auto - negotiation 0 = cannot perform auto - negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/l h 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui). k endin communication?s oui is 0010a1 ( hex). ro 0022h register 3h ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24th bits of the organizationally unique identifier (oui). k endin communication?s oui is 0010a1 (hex). ro 0001_01 3.9:4 model number six - bit manufacturer?s model number ro 01_0110 3.3:0 revision number four - bit manufacturer?s revision number ro indicates silicon revision register 4h ? auto - negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability rw 0 4.14 reserved reserve d ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved reserved ro 0 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 32 revision 1.1 register description (continued) address name description mode (1) default register 4h ? auto - negotiation advertisement 4.11:10 pause [00] = no pa use [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause rw 00 4.9 100base -t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability rw set by the anen_speed strapping pin. see the ? strapping options ? section for details. 4.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability rw set by the anen_speed strapping pin. s ee the ? strapping options ? section for details. 4.6 10base -t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability rw 1 4.5 10base -t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps ha lf - duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5h ? auto - negotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetri c pause ro 00 5.9 100base -t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability ro 0 5.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half -du plex capability ro 0 5.6 10base -t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability ro 0 5.5 10base -t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability ro 0 5.4:0 selector field [00001] = iee e 802.3 ro 0_0001 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 33 revision 1.1 register description (continued) address name description mode (1) default register 6h ? auto - negotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local dev ice does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto - negotiation able 1 = link partner has auto - negotiation capability 0 = link partner does not have auto - negotia tion capability ro 0 register 7h ? auto - negotiation next page 7.15 next page 1 = additional next pages will follow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic 1 0 = logic 0 ro 0 7.10:0 message field 11- bit wide field to encode 2048 messages rw 000_0000_0001 register 8h ? link partner next page ability 8.15 next page 1 = additional next pages will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page r o 0 8.12 acknowledge2 1 = can act on the information 0 = cannot act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic 0 0 = previous value of transmitted link code word equal to logic 1 ro 0 8.10:0 me ssage field 11- bit wide field to encode 2048 messages ro 000_0000_0000 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 34 revision 1.1 register description (continued) address name description mode (1) default register 10h ? digital reserved control 10.15:5 reserved reserved rw 0000_0000_000 10.4 pll off 1 = turn p ll off automatically in edpd mode 0 = keep pll on in edpd mode. see also register 18h, bit [11] for edpd mode rw 0 10.3:0 reserved reserved rw 0000 register 11h ? afe control 1 11.15:6 reserved reserved rw 0000_0000_00 11.5 slow - oscillator mode enable slow - oscillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on - chip slow oscillator when the ksz8081rna/rnd device is not in use after power -up. 1 = enable 0 = disable this bit automatically sets software power - down to the analog side when enabled. rw 0 11.4:0 reserved reserved rw 0_0000 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h register 16h ? operation mode strap override 16.15 reserved facto ry mode if rxer (pin 17) latches in a pull - up value at the de - assertion of re set, write a ?0? to this bit to clear reserved factory mode. rw set by the pull - up / pull - down value of rxer ( pin 17 ). 16.1 4 :11 reserved reserved rw 000_0 16.10 reserved reserve d ro 0 16.9 b- cast_off override 1 = override strap - in for b - cast_off if bit is ?1?, phy address 0 is non - broadcast. rw 0 16.8:7 reserved reserved rw 0_0 16.6 rmii b -to -b override 1 = override strap - in for rmii back -to - back mode (also set bit 1 of this register to ?1?) rw 0 16.5 nand tree override 1 = override strap - in for nand tree mode rw 0 16.4:2 reserved reserved rw 0_00 16.1 rmii override 1 = override strap - in for rmii mode rw 1 16.0 reserved reserved rw 0 register 17h ? operation mode strap st atus 17.15:13 phyad[2:0] strap - in status [000] = strap to phy address 0 [011] = strap to phy address 3 the ksz8081rna/rnd supports only phy addresses 0h and 3h. ro 17.12:2 reserved reserved ro 17.1 rmii strap - in status 1 = strap to rmii mode ro micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 35 revision 1.1 reg ister description (continued) address name description mode (1) default register 17h ? operation mode strap status 17.0 reserved reserved ro register 18h ? expanded control 18.15:12 reserved reserved rw 0000 18.11 edpd disabled energy - detect power -dow n mode 1 = disable 0 = enable see also register 10h, bit [4] for pll off. rw 1 18.10:0 reserved reserved rw 000_0000_0000 register 1bh ? interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect faul t interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link - down interrupt enable 1= enable link - down interrupt 0 = disable link - down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link - up interrupt enable 1 = enable link - up interrupt 0 = disable link - up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occur ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occur ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/sc 0 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge o ccurred 0 = link partner acknowledge did not occur ro/sc 0 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 36 revision 1.1 register description (continued) address name description mode (1) default register 1bh ? interrupt control/status 1b.2 link - down interrupt 1 = link - down occurred 0 = link - down did not occur ro/ sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/sc 0 1b.0 link - up interrupt 1 = link - up occurred 0 = link - up did not occur ro/sc 0 register 1dh ? linkmd control/status 1d.15 cable diagnostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self - cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal c ondition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ro 0 1d.11:9 reserved reserved rw 000 1d.8:0 cable fault counter distance to fault ro 0_0000_0000 register 1eh ? phy control 1 1e.15:10 reserved reserved ro 0000_00 1e.9 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity status 1 = polarity is reversed 0 = polarity is not reversed ro 1e.6 reserved reserved ro 0 1e.5 mdi/mdi - x state 1 = mdi - x 0 = mdi ro 1e.4 energy detect 1 = signal present on receive diff erential pair 0 = no signal detected on receive differential pair ro 0 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 37 revision 1.1 register description (continued) address name description mode (1) default register 1eh ? phy control 1 1 e.2:0 operation mode indication [000] = still in auto - negotiation [001] = 10base - t half - duplex [010] = 100base - tx half - duplex [011] = reserved [100] = reserved [101] = 10base - t full - duplex [110] = 100base - tx full - duplex [111] = reserved ro 000 register 1f h ? phy control 2 1f.15 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode rw 1 1f.14 mdi/mdi - x select when auto mdi/mdi - x is disabled, 1 = mdi - x mode transmit on rxp,rxm (pins 4, 3) and receive on txp,txm (pins 6, 5) 0 = mdi mode trans mit on txp,txm (pins 6, 5) and receive on rxp,rxm (pins 4, 3) rw 0 1f.13 pair swap disable 1 = disable auto mdi/mdi - x 0 = enable auto mdi/mdi - x rw 0 1f.12 reserved reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit byp asses the control logic and allows the transmitter to send a pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = disable power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7 rmii reference clock select 1 = for ksz8081rna, clock input to xi (pin 8) is 50mhz for rmii ? 50mhz clock mode. for ksz8081rnd, clock input to xi (pin 8) is 25mhz for rmii ? 25mhz clock code. 0 = for ksz8081rna, clock input to xi (pin 8) is 25mhz for rmii ? 25mhz clock code. for ksz8081rnd, clock input to xi (pin 8) is 50mhz for rmii ? 50mhz clock mode. rw 0 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 38 revision 1.1 register description (continued) address name descri ption mode (1) default register 1fh ? phy control 2 1f.6 reserved reserved rw 0 1f.5:4 led mode [00] = led0: link/activity [01] = led0: link [10], [11] = reserved rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 1f. 2 remote loopback 1 = remote (analog) loopback is enabled 0 = normal mode rw 0 1f.1 reserved reserved rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 39 revision 1.1 absolute maximum ratings (1) supply voltage (v in ) (v dd_1.2 ) .................................................. ? 0.5v to +1.8v (v ddio, v dda_3.3 ) ....................................... ? 0.5v to +5.0v input voltage (all inputs) .............................. ? 0.5v to +5.0v output voltage (all outputs) ......................... ? 0.5v to +5.0v lead temperature (soldering, 10sec.) ....................... 260c storage temperature (t s ) ......................... ? 55c to +150c operating ratings (2) supply voltage (v ddi o_3.3, v dda_3.3 ) .......................... +3.135v to +3.465v (v ddio_2.5 ) ........................................ +2.375v to +2.625v (v ddio_1.8 ) ........................................ +1.710v to +1.890v ambient temperature (t a , commercial) ...................................... 0c to +70c (t a , industrial) ....................................... ? 40c to +85c maximum junction temperature (t j max.) ................ 125c thermal resistance ( ja ) .................................... 49 .22 c/w thermal resistance ( jc ) .................................... 25.65 c/w electrical characteristics ( 3 ) symbol parameter condition min . typ . max . units supply current (v ddio , v dda_3.3 = 3.3v) (4) i dd1_3.3v 10base -t full - duplex traffic @ 100% utilization 41 ma i dd2_3.3v 100base -tx full - duplex traffic @ 100% utilization 47 ma i dd3_3.3v edpd mode ethernet cable disconnected (reg. 18h.11 = 0) 20 ma i dd4_3.3v power - down mode software power - down (reg. 0h.11 = 1) 4 ma cmos level inputs v ih input high voltage v ddio = 3.3v 2.0 v v ddio = 2.5v 1.8 v v ddio = 1.8v 1.3 v v il input low voltage v ddio = 3.3v 0.8 v v ddio = 2.5v 0.7 v v ddio = 1.8v 0.5 v |i in | input current v in = gnd ~ vddio 10 a cmos level outputs v oh output high voltage v ddio = 3.3v 2.4 v v ddio = 2.5v 2.0 v v ddio = 1.8v 1.5 v v ol output low voltage v ddio = 3.3v 0.4 v v ddio = 2.5v 0.4 v v ddio = 1.8v 0.3 v |i oz | output tri - state leakage 10 a led output i led output drive current led 0 pin 8 ma notes: 1. exceeding t he absolute maximum rating can damage the device. stresses greater than the absolute maximum rating can cause permanent damage to the device. operation of the device at these or any other conditions above those specified in the operating section s of this s pecification is not implied. maximum conditions for extended periods may affect reliability. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25c. specificatio n is for packaged product only. 4. current consumption is for the single 3.3v supply ksz8081rna/rnd device only, and includes the transmit driver current and the 1.2v supply voltage (v dd_1.2 ) that are supplied by the ksz8081rna/rnd. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 40 revision 1.1 electrical characteristics (3) symbol parameter condition min. typ. max. units all pull - up/pul l - down pins (including strapping pins) pu internal pull - up resistance v ddio = 3.3v 30 45 73 k v ddio = 2.5v 39 61 102 k v ddio = 1.8v 48 99 178 k pd internal pull - down resistance v ddio = 3.3v 26 43 79 k v ddio = 2.5v 34 59 113 k v ddio = 1.8 v 53 99 200 k 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % output jitter peak -to - peak 0.7 ns 10base - t transmit (measured differentially after 1:1 transformer) v p peak differential o utput voltage 100 termination across differential output 2.2 2.8 v jitter added peak -to - peak 3.5 ns t r , t f rise/fall time 25 ns 10base - t receive v sq squelch threshold 5mhz square wave 400 mv transmitter ? drive setting v set reference voltage of i set r(i set ) = 6.49 k 0.65 v ref_clk output 50mhz rmii clock output jitter peak -to - peak (applies only to rmii ? 25 mhz clock mode ) 300 ps 100mbps mode ? industrial applications parameters t llr link loss reaction (indication) time link loss detected at receive differential inputs to phy signal indication time for each of the following: 1 . for led mode 01, link led output changes from low (link - up) to high (link - down). 2 . intrp pin asserts for link - down status change. 4.4 s micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 41 revision 1.1 timing diagrams rmii timing figure 10 . rmii timing ? data received from rmii figure 11 . rmii timing ? data input to rmii timing parameter description min. typ. max. unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 7 10 13 ns table 10 . rmii timing parameters ? ksz8081rna/rnd (25mhz input to xi pin, 50mhz output from ref_clk pin) timing parameter description min. typ. max. unit t cyc clock cycle 20 ns t 1 s etup time 4 ns t 2 hold time 2 ns t od output delay 8 11 13 ns table 11 . rmii timing parameters ? ksz8081rna/rnd (50mhz input to xi pin) micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 42 revision 1.1 auto - negotiation timing figure 12 . auto - negotiation fast l ink pulse (flp) timing timing parameter description min. typ. max. units t btb flp b urst to flp b urst 8 16 24 ms t flpw flp b urst width 2 ms t pw clock/data p ulse width 100 ns t ctd clock p ulse to d ata p ulse 55.5 64 69.5 s t ctc clock pulse to c lo ck p ulse 111 128 139 s number of clock/d ata p ulse s per flp b urst 17 33 table 12 . auto - negotiation fast link pulse (flp) timing parameters micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 43 revision 1.1 mdc/mdio timing figure 13 . mdc/mdio timing timing parameter description min. typ. max. unit t p mdc period 400 ns t md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc 5 ns table 13 . mdc/mdio timing parameters micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 44 revision 1.1 power - u p/ r eset timing the ksz8081rna/rnd reset timing requirement is summarized in figure 14 and table 14. figur e 14 . power -u p/reset timing parameter description min. max. units t vr supply voltage (v ddio, v dda_3.3 ) rise time 300 s t sr stable supply voltage (v ddio, v dda_3.3 ) to reset high 10 ms t cs configuration setup time 5 ns t c h configuration hold time 5 ns t rc reset to strap - in pin output 6 ns table 14 . power -u p/reset timing parameters the supply voltage ( v ddio and v dda_3.3 ) power - up waveform should be monotonic . t he 300 s minimum rise time is fr om 10% to 90%. for warm reset, the reset (rst#) pin should be asserted low for a minimum of 500 s. the strap - in pin values are read and updated at the de - assertion of reset. after the de - assertion of reset, wait a minimum of 100 s before starting prog ram ming on the miim (mdc/mdio) i nterface. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 45 revision 1.1 reset circuit figure 15 shows a reset circuit recommended for powering up the ksz8081rna/rnd if reset is triggered by the power supply. figure 15 . recommended reset circuit figure 16 shows a reset circuit recommended for applications where reset is driven by another device ( for example , the cpu or an fpga). at power - on- reset, r, c , and d1 provide the nec essary ramp rise time to reset the ksz8081rna/rnd device. the rst_out_n from the cpu/fpga prov ides the warm reset after power - up. figure 16 . recommended reset circuit for i nterfacing with cpu/fpga reset output micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 46 revision 1.1 reference cir cuits ? led strap-i n pins the pull - up, float , and pull - down reference circuits for the led0/ anen_speed stra pping pin are shown in figure 17 for 3.3v and 2.5v vddio. figure 17 . referenc e circuits for led strapping pins for 1.8v vddio, led indication support is not recommended due to the low voltage. without the led indicator, the anen_speed strapping pin is functional with a 4.7 k p ull - up to 1.8v vddio or float for a value of ?1?, and with a 1.0 k pull - down to ground for a value of ?0?. micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 47 revision 1.1 reference clock ? connection and selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the ksz8081rna/rnd . for the ksz8081rna/rnd in rmii ? 25mhz clock m ode, the reference clock is 25 mhz . the reference clock connections to xi (pin 8 ) and xo (pin 7 ), and the reference clock selection criteria , are provided in figure 18 and table 15. figure 18 . 25mhz crystal /oscillator reference clock connection characteristics value units frequency 25 mhz frequency tolerance (max . ) 50 p pm c rystal series resistance (typ.) 40 crystal load capacitance (typ.) 16 pf table 15 . 25mhz crystal / reference clock selection criteria for the ksz8081rna/rnd in rmii ? 50mhz clock mode, the reference clock is 50 mhz. the refer ence clock connection to xi (pin 8 ) , and the reference clock selection criteria are provided in figure 19 and table 16. figure 19 . 50mhz oscil lator reference clock connection characteristics value units frequency 50 mhz frequency tolerance (max) 50 ppm table 16 . 50mhz oscillator / reference clock selection criteria micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 48 revision 1.1 magnetic ? connection and selection a 1:1 isolat ion transformer is required at the line interface. use one with integrated common - mode chokes for designs exceeding fcc requirements. the ksz8081rna/rnd design incorporates voltage - mode transmit drivers and on - chip terminations. with the voltage - mode imp lementation, the transmit drivers supply the common - mode voltages to the two differential pairs. therefore, the two transformer center tap pins on the ksz8081rna/rnd side should not be connected to any power supply source on the board ; instead , the center tap pins should be separated from one another and connected through separate 0.1 f common - mode capacitors to ground. separation is required because the common - mode voltage is different between transmitting and receiving differential pairs . figure 20 shows the typical magnetic interface circuit for the ksz8081rna/rnd . figure 20 . typical magnetic interface circuit micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 49 revision 1.1 table 17 lists recommended mag netic characteristics. parameter value test condition turns ratio 1 ct : 1 ct open - circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss ( typ .) ? 1. 1 db 100 k hz to 100mhz hipot (min.) 1500vrms table 17 . magnetics selection criteria table 18 is a list of compatible single - port magnetics with separated trans former center tap pins on the phy chip side that can be used with the ksz8081rna/rnd . manufacturer part number temper ature range magnetic + rj -45 bel fuse s558 - 5999-u7 0c to 70c no bel fuse si - 46001-f 0c to 70c yes bel fuse si - 50170-f 0c to 70c yes delta lf8505 0c to 70c no halo hfj11 - 2450e 0c to 70c yes halo tg110 - e055n5 ? 40c to 85c no lankom lf - h41s -1 0c to 70c no pulse h1102 0c to 70c no pulse h1260 0c to 70c no pulse hx1188 ? 40c to 85c no pulse j00 - 0014 0c to 70c yes pulse jx0011d21nl ? 40c to 85c yes tdk tla - 6t718a 0c to 70c yes transpower hb726 0c to 70c no wurth/midcom 000- 7090- 37r - lf1 ? 40c to 85c no table 18 . compatible single -p ort 10/100 magnetics micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 50 revision 1.1 recommended land pattern figure 21 . recommended land pattern, 2 4 - pin (4mm 4 mm) qfn red circles indicate ther mal vias. they should be 0.350mm in diameter and be connected to the gnd plane for maximum thermal performance. green rectangles (with shaded area) indicate solder stencil openings on the expos ed pad area. they should be 1.00 x 1.00mm in size, 1.20 mm pitch . micrel, inc. ksz8081rna/ksz8081rn d february 6, 2014 51 revision 1.1 package information (1) 24- pin (4 mm 4 mm) qfn note: 1. package information is correct as of the publication date. for updates and most current information, go to www.micrel.com . (micrel note body) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptio ns at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a product can reasonably be expected to result in personal in jury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signific ant injury to the user. a p urchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk an d purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2012 micrel, incorporated. |
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